In a semiconductor process, multiple semiconductor element segments (light emitting element segments) arranged and disposed on a semiconductor wafer are formed simultaneously through photolithography, vacuum deposition, etc. A dividing region for dividing the light emitting element segments is formed between the simultaneously formed light emitting element segments, and a dividing line along the center of this dividing region is cut vertically and horizontally by dicing, etc., thereby dividing the light emitting element segments into individual rectangular semiconductor chips (light emitting elements).
The area of the light emitting elements has been downsized for the cost reduction of the light emitting element, but the smaller the size of the light emitting element becomes, the larger the area of the dividing region in the semiconductor wafer becomes. Hence, in order to increase the number of the light emitting elements obtainable from the semiconductor wafer, there is a technical problem to effectively narrow down the dividing region.
For example, Patent Literature 1 discloses a technology which forms the semiconductor wafer in such a way that the width of a vertical dividing region and that of a horizontal dividing region differ from each other, and which narrows down the width of the dividing region in a direction along the longer side of a semiconductor element (while the width of the shorter side is extended). Moreover, Patent Literature 2 discloses a semiconductor wafer that elongates the width of a dicing line which includes an alignment mark for a stepper. Furthermore, Patent Literature 3 discloses a technology of disposing the shorter side of the semiconductor element segment in the horizontal direction to an orientation flat where chipping of the semiconductor wafer is not likely to occur, thereby narrowing down the width of the dividing region along this shorter side.